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Many of the GD chips support two or even three can busses.
Would be nice to have support for that peripheral.
Should be as easy as taking the code from the STM core and moving it to the GD core.
On Mon, Jun 20, 2022, at 11:27 PM, CzokNorris wrote:
Many of the GD chips support two or even three can busses.
Would be nice to have support for that peripheral.
Should be as easy as taking the code from the STM core and moving it to the GD core.
Because of ST's restrictive licensing, we can't use code from their current cores.
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obra commentedon Jun 21, 2022
maxgerhardt commentedon Jun 21, 2022
Also linked to CommunityGD32Cores/gd32-pio-projects#7 -- I was about to tackle this.