mip.MSIP should not be writable #247

Bug Description:

When executing a CSR write to mip using csrw mip, a7, NutShell incorrectly updates the MSIP bit (bit 3).

The rsicv specification is as follows:

Bits mip.MSIP and mie.MSIE are the interrupt-pending and interrupt-enable bits for machine-level
software interrupts. MSIP is read-only in mip, and is written by accesses to memory-mapped control
registers, which are used by remote harts to provide machine-level interprocessor interrupts. A hart
can write its own MSIP bit using the same memory-mapped control register. If a system has only one
hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through
external interrupts (MEI) instead, then mip.MSIP and mie.MSIE may both be read-only zeros.

Test program and log information: test_MSIP.zip

Inconsistent information:

Environment:

NutShell: commit e315a27