A complete from-scratch digital implementation of M. Morris Mano's Basic Computer, based on the architecture described in Computer System Architecture.
The entire computer is implemented in Logisim, with every major hardware component designed and connected from fundamental digital logic elements.
This project is a complete hardware-level implementation of Mano's Basic Computer, built from the ground up rather than assembled from pre-built CPU components.
This project implements the Basic Computer described by M. Morris Mano in Computer System Architecture.
The computer was built entirely from scratch in Logisim. Every major component was individually designed and integrated to reproduce the architecture described in the book.
The implementation includes:
- Complete processor datapath
- Registers
- Common bus
- Arithmetic and Logic Unit (ALU)
- Memory
- Instruction decoder
- Control unit
- Timing and sequencing logic
- Memory-reference instructions
- Register-reference instructions
- Input/output instructions
- Interrupt system
The goal of the project was to understand how a complete CPU can be constructed from fundamental digital logic components and how those components cooperate to execute machine instructions.
The implementation follows the architecture of Morris Mano's Basic Computer.
| Register | Size | Description |
|---|---|---|
| AR | 12-bit | Address Register |
| PC | 12-bit | Program Counter |
| DR | 16-bit | Data Register |
| AC | 16-bit | Accumulator |
| IR | 16-bit | Instruction Register |
| TR | 16-bit | Temporary Register |
| INPR | 8-bit | Input Register |
| OUTR | 8-bit | Output Register |
| SC | 4-bit | Sequence Counter |
| E | 1-bit | Extended accumulator / carry flip-flop |
| IEN | 1-bit | Interrupt Enable flip-flop |
| FGI | 1-bit | Input flag |
| FGO | 1-bit | Output flag |
One of the main goals of this project was to build the computer from the logic level upward.
No pre-built CPU, ALU, register bank, control unit, or processor core was used.
The computer was constructed using fundamental digital components such as:
- Logic gates
- Flip-flops
- Adders
- Multiplexers
- Decoders
- Counters
- Registers
- Bus logic
- Memory
- Clock and timing circuitry
These components were combined hierarchically to construct the complete computer.
The overall design can be viewed as:
Logic Gates
│
▼
Flip-Flops / Basic Logic
│
▼
Registers / Adders / Multiplexers / Decoders
│
▼
ALU / Common Bus / Control Logic
│
▼
Datapath + Control Unit
│
▼
Mano Basic Computer
Each register required by Mano's architecture was implemented and connected individually.
The registers support the operations required by the processor, including:
- Loading
- Clearing
- Incrementing where required
- Controlled data transfer
- Clocked state updates
- Bus interaction
The processor uses a common bus for transferring data between registers and other parts of the datapath.
The bus was implemented using multiplexing and control logic.
Examples of register-transfer operations include:
AR ← Bus
PC ← Bus
DR ← Bus
AC ← Bus
IR ← Bus
TR ← Bus
The bus control signals determine which register places data onto the bus and which register receives it.
The ALU was constructed from basic digital logic components.
It performs the arithmetic and logical operations required by the Basic Computer, including:
- AND
- ADD
- Increment
- Complement
- Clear
- Shift / circulate operations
The E flip-flop is used for carry and rotate operations as specified by the architecture.
The control unit was designed from scratch and generates the control signals required to operate the processor.
It combines:
- Instruction decoding
- Timing signals
- Register control
- Bus selection
- ALU control
- Memory control
- I/O control
- Interrupt control
The control unit coordinates the individual hardware components and generates the required microoperations for each instruction.
The processor uses a sequence counter and timing signals to divide instruction execution into individual microoperations.
The general instruction cycle is:
Fetch
↓
Decode
↓
Indirect Address / Effective Address
↓
Execute
↓
Interrupt Check
↓
Next Instruction
Each stage is controlled by timing signals generated by the timing and sequencing circuitry.
The Basic Computer uses:
4096 × 16-bit memory
This provides:
- 4096 addressable words
- 12-bit addresses
- 16-bit data words
The memory system is connected to the Address Register, Data Register, common bus, and control circuitry according to Mano's architecture.
The implementation follows the instruction set defined in Mano's Basic Computer.
| Opcode | Instruction | Operation |
|---|---|---|
| 000 | AND | AC ← AC ∧ M[AR] |
| 001 | ADD | AC ← AC + M[AR] |
| 010 | LDA | AC ← M[AR] |
| 011 | STA | M[AR] ← AC |
| 100 | BUN | PC ← AR |
| 101 | BSA | M[AR] ← PC, AR ← AR + 1, PC ← AR |
| 110 | ISZ | M[AR] ← M[AR] + 1; skip if zero |
The I bit determines whether direct or indirect addressing is used.
| Instruction | Description |
|---|---|
| CLA | Clear AC |
| CLE | Clear E |
| CMA | Complement AC |
| CME | Complement E |
| CIR | Circulate right AC and E |
| CIL | Circulate left AC and E |
| INC | Increment AC |
| SPA | Skip if AC is positive |
| SNA | Skip if AC is negative |
| SZA | Skip if AC is zero |
| SZE | Skip if E is zero |
| HLT | Halt computer |
| Instruction | Description |
|---|---|
| INP | Input character into AC |
| OUT | Output character from AC |
| SKI | Skip if input flag is set |
| SKO | Skip if output flag is set |
| ION | Enable interrupts |
| IOF | Disable interrupts |
The processor executes instructions through a sequence of microoperations.
The instruction is retrieved from memory using the Program Counter.
Conceptually:
AR ← PC
IR ← M[AR]
PC ← PC + 1
The Instruction Register is decoded to determine:
- Instruction opcode
- Addressing mode
- Instruction type
The instruction is classified as a:
- Memory-reference instruction
- Register-reference instruction
- Input/output instruction
For memory-reference instructions using indirect addressing, the effective address is obtained from memory before the instruction is executed.
The control unit generates the required sequence of microoperations for the decoded instruction.
These operations control:
- Registers
- Common bus
- ALU
- Memory
- I/O circuitry
After instruction execution, the processor checks whether an interrupt request should be serviced.
If the required interrupt conditions are satisfied, the processor enters the interrupt cycle.
The interrupt mechanism described in Mano's Basic Computer is implemented as part of the processor.
The implementation includes:
- FGI — Input Flag
- FGO — Output Flag
- IEN — Interrupt Enable
- Interrupt detection
- Interrupt cycle
- Interrupt-related control signals
This allows the processor to respond to input/output events using the interrupt mechanism described in the architecture.
The project was designed to avoid treating CPU components as black boxes.
Instead, the implementation follows a bottom-up approach:
Basic Logic
↓
Digital Components
↓
Functional Units
↓
Datapath
↓
Control Unit
↓
Complete Computer
This makes the project useful for understanding the relationship between:
- Digital logic
- Computer organization
- Computer architecture
- Processor design
- Machine-level instruction execution
The project demonstrates how a functional CPU can be constructed from relatively simple digital building blocks.
The complete computer is implemented as a Logisim .circ circuit.
The circuit contains the complete processor and its supporting hardware.
Each major functional unit was designed individually and then integrated into the complete architecture.
The implementation does not rely on a pre-built CPU or processor core.
mano-basic-computer/
│
├── README.md
│
└── <logisim-circuit>.circ
- Logisim or a compatible Logisim distribution
- Basic understanding of digital logic and computer architecture
- Clone the repository.
git clone <repository-url>-
Open the
.circfile in Logisim. -
Initialize the processor.
-
Load a program into memory.
-
Start the clock / execution sequence.
-
Observe the processor execute the program.
You can inspect the internal registers, bus, ALU, control signals, timing signals, and memory while the computer is running.
This project was built to develop a practical understanding of:
- Digital logic design
- Computer architecture
- Computer organization
- CPU datapath design
- Register-transfer operations
- ALU construction
- Common bus architecture
- Memory organization
- Instruction decoding
- Control-unit design
- Timing and sequencing
- Microoperations
- Interrupt handling
- Machine-level instruction execution
The architecture implemented in this project is based on:
M. Morris Mano Computer System Architecture
This project is an independent educational implementation of the Basic Computer architecture described in the book.
Complete
The complete Basic Computer architecture described by M. Morris Mano has been implemented from scratch in Logisim.
This includes:
- Processor datapath
- Registers
- Common bus
- ALU
- Memory
- Instruction decoder
- Control unit
- Timing and sequencing
- Memory-reference instructions
- Register-reference instructions
- Input/output instructions
- Interrupt system
Built from scratch as an educational implementation of M. Morris Mano's Basic Computer.
This project is intended for educational and learning purposes.