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[API Proposal]: Arm64: FEAT_SHA3 #98692

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#126941
Closed
[API Proposal]: Arm64: FEAT_SHA3#98692
#126941
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api-approvedAPI was approved in API review, it can be implementedarch-arm64area-System.Runtime.Intrinsicsin-prThere is an active PR which will close this issue when it is merged
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11.0.0

Description

@a74nh
a74nh
opened on Feb 20, 2024

FEAT_SHA3 provides instructions to accelerate the SHA-3 hash algorithm. This set of instructions is described as
the SHA3 instructions.

The SHA-3 hash algorithm is based on a running digest of 1600 bytes, arranged as a five by five array of 64-bit registers. The Arm acceleration of these instructions is based on mapping the 25 64-bit values into 25 vector registers, with each 64-bit value occupying the same 64-bit element in each vector. A series of transformations is performed on these registers as part of a round of the SHA-3 hash calculation.

The SIMD nature of the vector registers means the acceleration can compute two parallel SHA3 hash calculations,
where one calculation is performed using the zeroth 64-bit element of each vector, and the other calculation is
performed using the first 64-bit element of each vector.

namespace System.Runtime.Intrinsics.Arm;

/// VectorT Summary
public abstract partial class Sha3 : AdvSimd /// Feature: FEAT_SHA3
{

  /// T: byte, ushort, uint, ulong, sbyte, short, int, long
  public static unsafe Vector128<T> BitwiseClearXor(Vector128<T> xor, Vector128<T> value, Vector128<T> mask); // BCAX

  public static unsafe Vector128<ulong> BitwiseRotateLeftBy1AndXor(Vector128<ulong> a, Vector128<ulong> b); // RAX1

  /// T: byte, ushort, uint, ulong, sbyte, short, int, long
  public static unsafe Vector128<T> Xor(Vector128<T> value1, Vector128<T> value2, Vector128<T> value3); // EOR3

  public static unsafe Vector128<ulong> XorRotateRight(Vector128<ulong> left, Vector128<ulong> right, [ConstantExpected] byte count); // XAR

  /// total method signatures: 4

}

Activity

  1. ghost added
    untriagedNew issue has not been triaged by the area owner
    on Feb 20, 2024
  2. ghost added
    area-System.Runtime.Intrinsics
    on Feb 20, 2024

  4. a74nh commented on Feb 20, 2024

    @a74nh
    a74nh
    on Feb 20, 2024
    ContributorAuthor
    /// Full API
public abstract partial class Sha3 : AdvSimd /// Feature: FEAT_SHA3
{
    /// BitwiseClearXor : Bit Clear and Exclusive OR performs a bitwise AND of the 128-bit vector in a source SIMD&FP register and the complement of the vector in another source SIMD&FP register, then performs a bitwise exclusive OR of the resulting vector and the vector in a third source SIMD&FP register, and writes the result to the destination SIMD&FP register.

    /// uint8x16_t vbcaxq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<byte> BitwiseClearXor(Vector128<byte> xor, Vector128<byte> value, Vector128<byte> mask);

    /// uint16x8_t vbcaxq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<ushort> BitwiseClearXor(Vector128<ushort> xor, Vector128<ushort> value, Vector128<ushort> mask);

    /// uint32x4_t vbcaxq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<uint> BitwiseClearXor(Vector128<uint> xor, Vector128<uint> value, Vector128<uint> mask);

    /// uint64x2_t vbcaxq_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<ulong> BitwiseClearXor(Vector128<ulong> xor, Vector128<ulong> value, Vector128<ulong> mask);

    /// int8x16_t vbcaxq_s8(int8x16_t a, int8x16_t b, int8x16_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<sbyte> BitwiseClearXor(Vector128<sbyte> xor, Vector128<sbyte> value, Vector128<sbyte> mask);

    /// int16x8_t vbcaxq_s16(int16x8_t a, int16x8_t b, int16x8_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<short> BitwiseClearXor(Vector128<short> xor, Vector128<short> value, Vector128<short> mask);

    /// int32x4_t vbcaxq_s32(int32x4_t a, int32x4_t b, int32x4_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<int> BitwiseClearXor(Vector128<int> xor, Vector128<int> value, Vector128<int> mask);

    /// int64x2_t vbcaxq_s64(int64x2_t a, int64x2_t b, int64x2_t c) : "BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<long> BitwiseClearXor(Vector128<long> xor, Vector128<long> value, Vector128<long> mask);


    /// BitwiseRotateLeftBy1AndXor : Rotate and Exclusive OR rotates each 64-bit element of the 128-bit vector in a source SIMD&FP register left by 1, performs a bitwise exclusive OR of the resulting 128-bit vector and the vector in another source SIMD&FP register, and writes the result to the destination SIMD&FP register.

    /// uint64x2_t vrax1q_u64(uint64x2_t a, uint64x2_t b) : "RAX1 Vd.2D,Vn.2D,Vm.2D"
  public static unsafe Vector128<ulong> BitwiseRotateLeftBy1AndXor(Vector128<ulong> a, Vector128<ulong> b);


    /// Xor : Three-way Exclusive OR performs a three-way exclusive OR of the values in the three source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

    /// uint8x16_t veor3q_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<byte> Xor(Vector128<byte> value1, Vector128<byte> value2, Vector128<byte> value3);

    /// uint16x8_t veor3q_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<ushort> Xor(Vector128<ushort> value1, Vector128<ushort> value2, Vector128<ushort> value3);

    /// uint32x4_t veor3q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<uint> Xor(Vector128<uint> value1, Vector128<uint> value2, Vector128<uint> value3);

    /// uint64x2_t veor3q_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<ulong> Xor(Vector128<ulong> value1, Vector128<ulong> value2, Vector128<ulong> value3);

    /// int8x16_t veor3q_s8(int8x16_t a, int8x16_t b, int8x16_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<sbyte> Xor(Vector128<sbyte> value1, Vector128<sbyte> value2, Vector128<sbyte> value3);

    /// int16x8_t veor3q_s16(int16x8_t a, int16x8_t b, int16x8_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<short> Xor(Vector128<short> value1, Vector128<short> value2, Vector128<short> value3);

    /// int32x4_t veor3q_s32(int32x4_t a, int32x4_t b, int32x4_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<int> Xor(Vector128<int> value1, Vector128<int> value2, Vector128<int> value3);

    /// int64x2_t veor3q_s64(int64x2_t a, int64x2_t b, int64x2_t c) : "EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B"
  public static unsafe Vector128<long> Xor(Vector128<long> value1, Vector128<long> value2, Vector128<long> value3);


    /// XorRotateRight : Exclusive OR and Rotate performs a bitwise exclusive OR of the 128-bit vectors in the two source SIMD&FP registers, rotates each 64-bit element of the resulting 128-bit vector right by the value specified by a 6-bit immediate value, and writes the result to the destination SIMD&FP register.

    /// uint64x2_t vxarq_u64(uint64x2_t a, uint64x2_t b, const int imm6) : "XAR Vd.2D,Vn.2D,Vm.2D,imm6"
  public static unsafe Vector128<ulong> XorRotateRight(Vector128<ulong> left, Vector128<ulong> right, [ConstantExpected] byte count);


  /// total method signatures: 18
  /// total method names:      4
}


  /// Total ACLE covered across API:      18

  5. a74nh commented on Feb 20, 2024

    @a74nh
    a74nh
    on Feb 20, 2024
    ContributorAuthor

    This adds the API for FEAT_SHA3. It complements the FEAT_SVE_SHA3 API which is specified in #94425.

    Note this is a NEON (AdvSimd) extension. It is not a SVE extension.

  6. a74nh commented on Feb 20, 2024

    @a74nh
    a74nh
    on Feb 20, 2024
    ContributorAuthor

    @tannergooding : As requested, the API for SHA3. SVE versions of BitwiseRotateLeftBy1AndXor exist in SVE_SHA3 and the other ones exist in SVE2

  7. tannergooding
    added
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    and removed
    untriagedNew issue has not been triaged by the area owner
    on Feb 20, 2024
  8. BruceForstall
    added
    arch-arm64
    on Feb 27, 2024
  9. tannergooding
    added this to the Future milestone on May 1, 2024
  10. tannergooding
    added
    api-suggestionEarly API idea and discussion, it is NOT ready for implementation
    and removed
    api-ready-for-reviewAPI is ready for review, it is NOT ready for implementation
    on Aug 20, 2024
  11. a74nh
    added
    api-ready-for-reviewAPI is ready for review, it is NOT ready for implementation
    and removed
    api-suggestionEarly API idea and discussion, it is NOT ready for implementation
    on Nov 28, 2025
  12. a74nh
    modified the milestones: Future, 11.0.0 on Nov 28, 2025

  13. bartonjs commented on Jan 6, 2026

    @bartonjs
    bartonjs
    on Jan 6, 2026
    Member

    Video

    • BitwiseRotateLeftBy1AndXor(a, b) => BitwiseRotateLeftBy1AndXor(xor, rol1)
    namespace System.Runtime.Intrinsics.Arm;

/// VectorT Summary
public abstract partial class Sha3 : AdvSimd /// Feature: FEAT_SHA3
{

  /// T: byte, ushort, uint, ulong, sbyte, short, int, long
  public static unsafe Vector128<T> BitwiseClearXor(Vector128<T> xor, Vector128<T> value, Vector128<T> mask); // BCAX

  public static unsafe Vector128<ulong> BitwiseRotateLeftBy1AndXor(Vector128<ulong> xor, Vector128<ulong> rol1); // RAX1

  /// T: byte, ushort, uint, ulong, sbyte, short, int, long
  public static unsafe Vector128<T> Xor(Vector128<T> value1, Vector128<T> value2, Vector128<T> value3); // EOR3

  public static unsafe Vector128<ulong> XorRotateRight(Vector128<ulong> left, Vector128<ulong> right, [ConstantExpected] byte count); // XAR

  /// total method signatures: 4
}
  14. bartonjs
    added
    api-approvedAPI was approved in API review, it can be implemented
    and removed
    api-ready-for-reviewAPI is ready for review, it is NOT ready for implementation
    on Jan 6, 2026
  15. a74nh
    added a commit that references this issue on Apr 15, 2026

    Add SHA3 and SVE SHA3 APIs

    c84f28a
  16. dotnet-policy-service
    added
    in-prThere is an active PR which will close this issue when it is merged
    on Apr 15, 2026
  17. tannergooding
    added a commit that references this issue on Jun 29, 2026

    Add SHA3 and SVE SHA3 APIs (#126941)

    21b722d
  18. tannergooding
    closed this as completedin #126941on Jun 29, 2026
  19. eiriktsarpalis
    added a commit that references this issue on Jul 15, 2026

    Add SHA3 and SVE SHA3 APIs (#126941)

    a9bc65f
  20. github-actions
    locked and limited conversation to collaborators on Jul 30, 2026
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