Skip to content

arm64: Add InterleavingXorEvenOdd & InterleavingXorOddEven - #116525

Merged
kunalspathak merged 4 commits into
dotnet:mainfrom
jonathandavies-arm:upstream/sve/bit-manipulate
Jun 13, 2025
Merged

arm64: Add InterleavingXorEvenOdd & InterleavingXorOddEven#116525
kunalspathak merged 4 commits into
dotnet:mainfrom
jonathandavies-arm:upstream/sve/bit-manipulate

Conversation

@jonathandavies-arm

@jonathandavies-arm jonathandavies-arm commented Jun 11, 2025

Copy link
Copy Markdown
Contributor

@dotnet-policy-service dotnet-policy-service Bot added the community-contribution Indicates that the PR has been added by a community member label Jun 11, 2025
@jonathandavies-arm

jonathandavies-arm commented Jun 11, 2025

Copy link
Copy Markdown
Contributor Author

@a74nh @kunalspathak @dotnet/arm64-contrib

@dotnet-policy-service

dotnet-policy-service Bot commented Jun 11, 2025

Copy link
Copy Markdown
Contributor

Tagging subscribers to this area: @dotnet/area-system-runtime-intrinsics
See info in area-owners.md if you want to be subscribed.

@kunalspathak kunalspathak mentioned this pull request Jun 11, 2025
Closed
kunalspathak
kunalspathak reviewed Jun 11, 2025
View reviewed changes
Comment thread src/coreclr/jit/hwintrinsiclistarm64sve.h
HARDWARE_INTRINSIC(Sve2, BitwiseSelect, -1, 3, {INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, BitwiseSelectLeftInverted, -1, 3, {INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, BitwiseSelectRightInverted, -1, 3, {INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)

@kunalspathak kunalspathak Jun 11, 2025

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)

kunalspathak
kunalspathak reviewed Jun 11, 2025
View reviewed changes
Comment thread src/coreclr/jit/hwintrinsiclistarm64sve.h
HARDWARE_INTRINSIC(Sve2, BitwiseSelectLeftInverted, -1, 3, {INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, BitwiseSelectRightInverted, -1, 3, {INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)

@kunalspathak kunalspathak Jun 11, 2025

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)

@a74nh a74nh Jun 13, 2025

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This one is RMW.

https://docsmirror.github.io/A64/2023-09/eortb_z_zz.html
"placing the result in the odd-numbered elements of the destination vector"

The input odd to the C# API is used as the destination register.

@kunalspathak kunalspathak Jun 13, 2025

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ah, the way I read RMW is if the manual has something like "Is the name of source and destination vector".

image

I think this API is unique in a way, where we are passing destination as an input to the API and hence that qualifies for RMW.

kunalspathak
kunalspathak reviewed Jun 11, 2025
View reviewed changes
Comment thread ...raries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs Outdated
public static Vector<ulong> InterleavingXorOddEven(Vector<ulong> even, Vector<ulong> left, Vector<ulong> right) { throw new PlatformNotSupportedException(); }


public static Vector<byte> InterleavingXorEvenOdd(Vector<byte> odd, Vector<byte> left, Vector<byte> right) { throw new PlatformNotSupportedException(); }

@kunalspathak kunalspathak Jun 11, 2025

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

All entries from this point onwards are redundant and should be removed. That is the reason builds are failing.

kunalspathak
kunalspathak suggested changes Jun 11, 2025
View reviewed changes

@kunalspathak kunalspathak left a comment

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Please fix the build

@kunalspathak

kunalspathak commented Jun 12, 2025

Copy link
Copy Markdown
Contributor

There are test failures that needs addressing:

14:17:06.273 Running test: _Sve2_ro::JIT.HardwareIntrinsics.Arm._Sve2.Program.Sve2_InterleavingXorEvenOdd_byte()

Assert failure(PID 33 [0x00000021], Thread: 33 [0x0021]): Assertion failed 'unreached' in 'JIT.HardwareIntrinsics.Arm._Sve2.SimpleTernaryOpTest__Sve2_InterleavingXorEvenOdd_byte:RunBasicScenario_UnsafeRead():this' during 'Generate code' (IL size 137; hash 0x9e1e953e; FullOpts)

    File: /__w/1/s/src/coreclr/jit/emitarm64sve.cpp:6912
    Image: /root/helix/work/correlation/corerun

This was referenced Jun 12, 2025
Open
Open
Open
Open
@kunalspathak

kunalspathak commented Jun 13, 2025

Copy link
Copy Markdown
Contributor

/ba-g unrelated failures

kunalspathak
kunalspathak approved these changes Jun 13, 2025
View reviewed changes

@kunalspathak kunalspathak left a comment

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@kunalspathak
kunalspathak merged commit e366255 into dotnet:main Jun 13, 2025
@github-actions github-actions Bot locked and limited conversation to collaborators Jul 14, 2025
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.

Reviewers

2 more reviewers
@a74nh a74nh a74nh left review comments
@kunalspathak kunalspathak kunalspathak approved these changes
Reviewers whose approvals may not affect merge requirements

Assignees

No one assigned

Labels

area-System.Runtime.Intrinsics community-contribution Indicates that the PR has been added by a community member

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

3 participants

@jonathandavies-arm @kunalspathak @a74nh